1. Field of the Invention
The present invention relates to an information processing device which reads instructions, buffers and executes instructions by pipeline processing, and more, particularly, to an information processing device which can reduce pipeline branching confusion when executing instruction sequences comprising branching instructions.
The present invention further relates to a memory bus access system for an information processing device which performs instruction fetching, instruction buffering and instruction decoding and execution by pipeline processing, and more particularly provides an efficient memory bus access system in a dual instruction fetch-type information processing system which performs parallel fetches for branching-generating side instruction sequence (referred to below as target side instruction sequence) and non-branching-generating side sequence (referred to below as sequential side instruction sequence).
2. Description of the Related Art
In information processing devices such as microprocessors which have employed pipeline processing, the reading of consecutive instruction sequences is performed successively without waiting for the execution of the individual instructions to be completed and the aforementioned instructions are buffered in an instruction buffer in such a way that there are no empty spaces in the execution cycle of the execution unit. However, when there is a branching instruction in the instruction sequence, the branch target instruction which has the possibility of being executed directly after this branching instruction becomes an instruction which does not follow in address from that branching instruction and the pipeline processing becomes confused, possibly reducing the efficiency of the information processing device.
For this reason, a method has been devised in which, if the information processing device has read a branching instruction, the branch target instruction sequence of that branching instruction is read in advance and buffered in an instruction buffer so that the confusion of the pipeline processing is minimized.
FIG. 13 shows a general constructional diagram of a conventional information processing device which performs such pipeline processing. A conventional information processing device has an instruction store 11 which stores the instruction sequence which is to be executed, an instruction buffering portion 12 which buffers the instruction read from the instruction store 11 and supplies to the decoder 21 the instruction whose execution is predicted, an instruction execution unit 20 provided with a decoder 21 which decodes the instruction supplied from the instruction buffering portion 12 and, if that instruction is a branching instruction, supplies a branch target address information (usual corresponding address) to a branch target address generating portion 16, a branch target address generating portion 16 which generates branch target addresses on the basis of the branch target address information which is received from the decoder 21 and a current address counter value, and an instruction reading request portion 17 which selects the instruction address to be read next from among the program counter values or branch target addresses received from the branch target address generating portion 16, or the addresses which have been requested from the instruction execution unit 20, supplies this address to the instruction store 11 and executes the instruction reading request.
In this type of information processing device, the decoder 21 decodes instructions which are supplied from the instruction buffering portion 12 and, if it detects that this instruction is a branching instruction, before the execution of this branching instruction, generated is the address of the branch target instruction which is a candidate to be the next instruction executed after this branching instruction, and this branch target instruction and the following instruction sequence can be read from the instruction store 11 in advance and buffered in the instruction buffering portion 12.
Therefore, when the branching to a branch target instruction has been determined as a result of the execution of a destination instruction, or when branching to a branch target instruction has been predicted, it is possible to process a branching instruction sequence at high speed with a low level of pipeline processing confusion by fetching this branch target instruction sequence from the instruction buffering portion 12 to the instruction execution unit 20.
In such a case, if instruction buffers for a plurality of sequences are provided in the instruction buffering portion 12, the branch target instruction sequence which is predicted to branch can be respectively buffered in the instruction buffers for a plurality of sequences and when it has been decided to perform branching the branch target instruction can be quickly fetched from the instruction buffer so that even when branching instructions consecutively follow, pipeline confusion can be reduced.
However, the constitution according to the prior art provides multi-sequence instruction buffers so that all the branch target instruction sequences which are predicted to branch can be buffered when there is a large number of branching instructions. This results in a disadvantageous increase in the hardware (instruction buffer) of the information processing device.
In addition, because in the information processing device according to the prior art it was necessary to decode branching instructions so as to generate branch target addresses in order to read branch target instruction sequences of the branching instructions, a large amount of processing time was required after reading the branching instruction until the branch target instruction corresponding to the aforementioned branching instruction was read, so that an instruction buffer for a plurality of instruction sequences could not be employed effectively.
The microprocessor (or information processing device) which relates to a second aspect of the invention and which performs instruction fetching, instruction buffering, instruction decoding and instruction execution by pipeline processing, performs high speed processing because it performs consecutive instruction sequence instruction fetching in advance, without any gaps in the execution stages in the execution unit. However, if there are branching instructions present inside the instruction sequence, which instruction sequence is fetched next varies depending on whether the system waits for the execution of that branching instruction and branches on the target side instruction sequence or whether it continues on the sequential side instruction sequence. As a result of this, empty spaces are generated temporally in the execution cycle of the execution unit. A target side instruction sequence is a branch target instruction sequence which is executed when branching is carried out as a result of a branching instruction being executed, and a sequential side instruction sequence is an instruction sequence which is executed when branching is not carried out as a result of a branching instruction being executed.
In order to avoid the abovementioned situations, dual instruction fetch-type information processing devices have been proposed, in which the CPU simultaneously outputs instruction fetch requests for both target side instruction sequence and sequential side instruction sequence and stores these instructions respectively in the 2 instruction buffers inside the CPUs. In these dual instruction fetch type devices, irrespective of whether the execution of the branching instruction results in branching to the target side or not, the next instruction sequence to be executed is buffered in the instruction buffer so that it is possible to minimize the execution stage delay associated with a new instruction fetch resulting from a predicted miss for the branching direction of the branching instruction.
In addition, a CPU which is a microprocessor uses a cache memory in order to perform high speed instruction fetching. Without using an external memory bus, CPU can not fetch instructions and data from a main memory of an external component in which instructions and data and the like are stored. Because the abovementioned memory bus access operations take a comparatively long time (a large number of pipeline cycles), a cache memory which stores instructions and data in the main memory is provided to the CPU. Usually, in the instruction fetch operation from the CPU, requests are made to the cache memory and fetched instructions are stored in the instruction buffer. When the cache memory does not store the fetched instruction with resulting a cache miss, a fetch object instruction is fetched from the main memory via the memory bus and is stored in both the instruction buffer and the cache memory.
However, when a main memory bus access which makes an instruction fetch from the main memory is performed frequently, the traffic on the memory bus increases. An increase in traffic on the memory busses causes delays in accessing the memory bus. In particular, it is undesirable that, in a stage before the branching instruction is executed, it takes a long time to fetch from the main memory instructions which have become necessary as a result of the execution of the branching instruction, due to the fact that target side or sequential side instructions which will probably not be executed are extracted from the main memory.